In recent years, semiconductor devices have been fabricated by defining feature sizes as small as around 100 nm or less through miniaturization using lithographic technology which employs, as exposing light, a beam at a wavelength of about 100 nm or less.
In such lithographic technology using short-wavelength light, a focal depth is extremely lowered so that it is inevitable to constantly keep planar a surface of a film formed on a substrate. In fabricating a next-generation semiconductor device (100 nm or less in feature size), therefore, the technology for planarizing the film on the substrate is significantly important. In the present specification, a substrate is defined as a substrate on which a semiconductor device is formed such as a semiconductor substrate, a liquid crystal substrate (LCD), or the like.
At present, CMP (Chemical Mechanical Polishing) is main-stream technology for planarizing a film in a device ranging in size from 0.13 μm to 0.25 μm. There has also been proposed a method for forming a planar film (planarized film) by laminating two films that have been formed preliminarily.
The description of the former CMP technology will be omitted since it has been well known. Instead, a description will be given herein below to a method for forming a planar film by laminating two films disclosed in, e.g., Japanese Laid-Open Patent Publication No. HEI 10-32198.
First, as shown in FIG. 20(a), a semiconductor device is constructed on a substrate 101 through a microfabrication process performed with respect thereto so that a stepped layer 102 is formed. Hereinafter, the substrate 101 formed with the stepped layer 102 will be termed a stepped substrate (101, 102).
Then, a plate 104 to which a film 103 formed as a sheet has been adhered preliminarily is disposed such that the sheet-like film 103 and the stepped layer 102 are opposed to each other.
Next, as shown in FIG. 20(b), the plate 104 formed with the sheet-like film 103 and the stepped substrate (101, 102) are brought closer to each other and pressed against each other with the application of heat.
Next, as shown in FIG. 20(c), only the plate 104 is peeled off, while the sheet-like film 103 is left on the stepped substrate (101, 102).
As a result, the sheet-like film 103 with a planar surface is formed on the stepped substrate (101, 102), as shown in FIG. 20(d). In FIG. 20(d), 105 denotes an unburied portion resulting from a depressed portion with a high aspect ratio formed between interconnect patterns which has remained unfilled.
However, the conventional method for fabricating a semiconductor device has the problem that a global step (a difference in height from the substrate surface between locations at a distance), e.g., a step between the points A and B in FIG. 20(d) occurs, though a step in a dense pattern portion adjacent the point A is removed and the film 103 can be planarized.
If the spacing between the interconnect patterns, i.e., the spacing between step patterns is 100 nm or less, the aspect ratio of a depressed portion formed between the step patterns is increased so that the depressed portion is not filled consistently.
Although the use of the CMP technology prevents the occurrence of the problem that a depressed portion with a high aspect ratio remains unfilled, the essential problem that the global step cannot be suppressed remains unsolved.